Method for implementing metal oxide semiconductor field effect transistor
US6274450A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 17, 1999 |
| Grant date | Aug 14, 2001 |
| Priority date | — |
| Expiry date | Sep 17, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/679
Abstract
A method for manufacturing metal oxide semiconductor field effect transistor is disclosed. The metal oxide semiconductor field effect transistor is formed by a specific fabricating process that disadvantages of thermal damage are effectively prevented. According to the method, first a substrate is provided. Second, an isolation and a well are formed in the substrate, and then a first dielectric layer, a conductive layer and an anti-reflection coating layer are formed on the substrate sequentially. Third, a gate is formed on the substrate, and then a source and a drain are formed in the substrate and a spacer is formed on the substrate. Fourth, both source and drain are annealed, and then a first salicide is formed on both source and drain. Fifth, a second dielectric layer is formed on the substrate and is planarized, where the anti-reflecting coating layer is totally removed and the conductive layer is partially removed. Sixth, a second salicide is formed on the conductive layer. Seventh, the spacer is removed and both a halo and a source drain extension are formed in substrate. Finally, a third dielectric layer is formed on second dielectric layer. Obviously, one main characterist…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.