Method of forming junction-leakage free metal silicide in a semiconductor wafer by amorphization of refractory metal layer
US6274511A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 24, 1999 |
| Grant date | Aug 14, 2001 |
| Priority date | — |
| Expiry date | Feb 24, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28518
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming ultra shallow junctions in a semiconductor wafer with reduced junction leakage arising from a silicidation process due to grain boundary induced stress induced junction spiking amorphizes the metal layer prior to annealing during silicidation. After the gate and source/drain junctions are formed in a semiconductor device, dopant or non-dopant material is implanted into the anamorphous metal layer that has been previously deposited over the gate and source/drain junctions. The ion implantation is performed at an energy level sufficient to amorphize the metal (e.g. cobalt), and substantially eliminate grain boundaries in the metal and release grain boundary induced stress. This prevents grain boundary stress induced diffusion of the metal during the first phase of the silicidation process, where the metal is the diffusing species. The silicide regions that are formed during subsequent annealing steps therefore do not exhibit junction spikes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.