Shielded channel transistor structure with embedded source/drain junctions
US6274913A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 5, 1998 |
| Grant date | Aug 14, 2001 |
| Priority date | — |
| Expiry date | Oct 5, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76283
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Microelectronic structures embodying the present invention include a silicon pillar contiguous with a bulk semiconductor, the pillar being surrounded by a shallow trench isolation insulator, which has been recessed to receive polysilicon and a superjacent layer of silicon deposited thereon. Source and drain (S/D) terminals are formed in the silicon of the recessed portions of the shallow trench isolation insulator. In this way the S/D terminals are substantially isolated from the body, thereby substantially reducing both parasitic junction capacitance and junction leakage currents. Isolation of S/D terminals in this way also reduces the degradation of effective channel length that can otherwise occur in MOSFETs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.