Single deposition layer metal dynamic random access memory
US6274928A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 8, 1997 |
| Grant date | Aug 14, 2001 |
| Priority date | — |
| Expiry date | May 8, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1815
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A 16 megabit (2.sup.24) or greater density single deposition layer metal Dynamic Random Access Memory (DRAM) part is described which allows for a die that fits within an industry-standard 300 ml wide SOJ (Small Outline J-wing) package or a TSOP (Thin, Small Outline Package) with little or no speed loss over previous double metal deposition layered 16 megabit DRAM designs. This is accomplished using a die architecture which allows for a single metal layer signal path, together with the novel use of a lead frame to remove a substantial portion of the power busing from the die, allowing for a smaller, speed-optimized DRAM. The use of a single deposition layer metal results in lower production costs, and shorter production time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.