Reduction of voltage stress across a gate oxide and across a junction within a high voltage transistor of an erasable memory device
US6275424A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2001 |
| Grant date | Aug 14, 2001 |
| Priority date | — |
| Expiry date | Jan 31, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention reduces the voltage across the gate oxide and across a junction of a high voltage MOSFET (Metal Oxide Semiconductor Field Effect Transistor) within an unselected block of an electrically erasable memory during an erase operation of a selected block of the electrically erasable memory. The drain node is coupled to each respective control gate node of a plurality of core cells disposed within a well. The present invention includes a voltage generator coupled to a gate node of the high voltage transistor and to the well having the core cells disposed therein. The present invention also includes a microcontroller that controls the voltage generator to ramp up a magnitude of a well voltage applied at the well from a start ramping time when the well voltage is at a start voltage to an end ramping time when the well voltage is at an end voltage. The mictocontroller also controls the voltage generator to couple the drain node of the high voltage MOSFET to a ground node having a ground voltage for a predetermined time period after the start ramping time. The well voltage reaches an intermediate voltage at the predetermined time period after the start ramping time. The …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.