Address decoder and method for ITS accelerated stress testing
US6275442A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 16, 2000 |
| Grant date | Aug 14, 2001 |
| Priority date | — |
| Expiry date | May 16, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A decoder circuit in a memory system accepts as inputs a clock signal and a plurality of address lines and produces as outputs a plurality of decode lines, such as word lines. The decoder circuit comprises a plurality of pre-decoding circuits, a plurality of latches, and a plurality of AND gates. Each pre-decoding circuit is connected to the clock signal and a unique combination of a subset of the plurality of address lines and their complements. Each pre-decoding circuit produces an output that is set in response to a unique state of the respective subset of the plurality of address lines. Each latch input is connected to an output of a respective one of the plurality of pre-decoding circuits. Each latch output is connected to an AND gate input, and each AND gate output is one of the plurality of decode lines. In another sense, the decoder comprises one or more stages of decoding logic and a set of latches. A first stage of decoding logic accepts the decoder inputs. The outputs of each non-final stage is an input to a subsequent stage. The set of latches are connected to the outputs of a particular non-final stage. A method for using the decoder processes a set of input signals, w…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.