Clock generation circuits and methods
US6275446A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 25, 2000 |
| Grant date | Aug 14, 2001 |
| Priority date | — |
| Expiry date | Aug 25, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Clock generator circuits containing a delay circuit having at least one delay element and at least one bypass are arranged to activate the bypass in response to a first logic level presented at the input of the delay circuit and to deactivate the bypass in response to a second logic level presented at the input of the delay circuit. Such clock generators are useful in synchronous memory devices for generating internal clock signals of fixed pulse width from an external clock signal. The internal clock signal is generated from a triggering event, such as a rising edge of the external clock signal, and has a pulse width determined by the delay time of the delay element. The first logic level is generated in response to the beginning of an output pulse of the clock generator while the second logic level is generated in response to the completion of an output pulse of the clock generator. Bypassing the delay element upon completion of an output pulse more quickly prepares the clock generator to receive the next triggering event.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.