Ebrahim Abedifard
128Patents
16h-index
28Co-inventors
86Inventor score
Filing activity: Jul 28, 2000 → Mar 22, 2025
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8574928B2 | MRAM fabrication method with sidewall cleaning | Electricity | 124 | Active |
| US8883520B2 | Redeposition control in MRAM fabrication process | Electricity | 64 | Active |
| US8792269B1 | Fast programming of magnetic random access memory (MRAM) | Physics | 57 | Active |
| US6975538B2 | Memory block erasing in a flash memory device | Physics | 51 | Expired |
| US6366524B1 | Address decoding in multiple-bank memory architectures | Physics | 43 | Expired |
| US7180781B2 | Memory block erasing in a flash memory device | Physics | 31 | Expired |
| US6496425B1 | Multiple bit line column redundancy | Physics | 25 | Expired |
| US6275446A | Clock generation circuits and methods | Physics | 24 | Expired |
| US6304488A | Current limiting negative switch circuit | Physics | 24 | Expired |
| US6445625B1 | Memory device redundancy selection having test inputs | Physics | 24 | Expired |
| US6504768B1 | Redundancy selection in memory devices with concurrent read and write | Physics | 24 | Expired |
| US6711056B2 | Memory with row redundancy | Physics | 22 | Expired |
| US6671214B2 | Methods of operating a multiple bit line column redundancy scheme having primary and redundant local and global bit lines | Physics | 21 | Expired |
| US8796795B2 | MRAM with sidewall protection and method of fabrication | Electricity | 18 | Active |
| US6665221B2 | Multiple bit line column redundancy with primary local and global bit lines and redundant local and global bit lines | Physics | 18 | Expired |
| US8724380B1 | Method for reading and writing multi-level cells | Physics | 17 | Active |
| US10395710B1 | Magnetic memory emulating dynamic random access memory (DRAM) | Electricity | 16 | Active |
| US6711701B1 | Write and erase protection in a synchronous memory | Physics | 15 | Expired |
| US6721206B2 | Methods of accessing floating-gate memory cells having underlying source-line connections | Electricity | 13 | Expired |
| US6774426B2 | Flash cell with trench source-line connection | Electricity | 12 | Expired |
| US7663925B2 | Method and apparatus for programming flash memory | Physics | 11 | Active |
| US8238145B2 | Shared transistor in a spin-torque transfer magnetic random access memory (STTMRAM) cell | Physics | 11 | Active |
| US6667910B2 | Method and apparatus for discharging an array well in a flash memory device | Physics | 10 | Expired |
| US6859392B2 | Preconditioning global bitlines | Physics | 9 | Expired |
| US6396728B1 | Array organization for high-performance memory devices | Physics | 9 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.