Bank selector circuit for a simultaneous operation flash memory device with a flexible bank partition architecture
US6275894A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 23, 1998 |
| Grant date | Aug 14, 2001 |
| Priority date | — |
| Expiry date | Sep 23, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bank selector circuit for a simultaneous operation flash memory device with a flexible bank partition architecture comprises a memory boundary option 18, a bank selector encoder 2 coupled to receive a memory partition indicator signal from the memory boundary option 18, and a bank selector decoder 3 coupled to receive a bank selector code from the bank selector encoder 2. The decoder 3, upon receiving a memory address, outputs a bank selector output signal to point the memory address to either a lower memory bank or an upper memory bank in the simultaneous operation flash memory device, in dependence upon the selected memory partition boundary.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.