Method of forming a sidewall spacer and a salicide blocking shape, using only one silicon nitride layer

US6277683A · kind A · utility

Assignee

• Chartered Semiconductor Manufacturing LTD · SG

Inventors

• Yelehanka Ramachandramurthy Pradeep · Singapore, SG
• Henry Gerung · Singapore, SG
• Jie Yu · Singapore, SG
• Pei Ching Lee · Singapore, SG

Key dates

• Filing date: Feb 28, 2000
• Grant date: Aug 21, 2001
• Expiry date: Feb 28, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A process for forming salicided CMOS devices, and non-salicide CMOS devices, on the same semiconductor substrate, using only one silicon nitride layer to provide a component for a composite spacer on the sides of the salicided CMOS devices, and to provide a blocking shape during metal silicide formation, for the non-salicided CMOS devices, has been developed. The process features the use of a disposable organic spacer, on the sides of polysilicon gate structures, used to define the heavily doped source/drain regions, for all CMOS devices. A silicon nitride layer, obtained via LPCVD procedures, at a temperature between 800 to 900.degree. C., is then deposited and patterned to provide the needed spacer, on the sides of the CMOS devices experiencing the salicide process, while the same silicon nitride layer is used to provide the blocking shape needed to prevent metal suicide formation for the non-salicided CMOS devices.