Computer system with improved memory access

US6279065A · kind A · utility

Assignee

• Compaq Computer Corporation · US

Inventors

• Kenneth T. Chin · Houston, US
• Jerome J. Johnson · Spring, US
• Phillip M. Jones · Spring, US
• Robert A. Lester · Houston, US
• Gary J. Piccirillo · Cypress, US
• C. Kevin Coffee · Pembroke, US
• Michael J. Collins · Tomball, US

Key dates

• Filing date: Jun 3, 1998
• Grant date: Aug 21, 2001
• Expiry date: Jun 3, 2018

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F13/4059
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A computer system includes a CPU and a memory device coupled by a bridge logic unit. CPU to memory write requests (including the data to be written) are temporarily stored in a queue in the bridge logic unit. The bridge logic unit preferably begins a write cycle to the memory device before all of the write data has been stored in the queue and available to the memory device. By beginning the memory cycle as early as possible, the total amount of time required to store all of the write data in the queue and then de-queue the data from the queue is reduced. Consequently, many CPU to memory write transactions are performed more efficiently and generally with less latency than previously possible.