Method for buried plate formation in deep trench capacitors
US6281068A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 14, 1999 |
| Grant date | Aug 28, 2001 |
| Priority date | — |
| Expiry date | Apr 14, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31138
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An improved method of forming the buried plate regions in deep trench capacitors used in DRAM memory semiconductor circuits in which the polymer used in the deep trench is etched down to the desired depth in a reactive ion etch tool using an O.sub.2 /CF.sub.4 chemistry. Since optical/interferometric etch end-point detection system can be used to monitor the etch back step in its totality, the quantity of the polymer remaining in deep trenches can be very accurately controlled, which in turn will produce a well controlled buried plate region during the out-diffusion step of the arsenic dopant contained in the arsenic doped silicon glass layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.