Semiconductor processing methods

US6281100A · kind A · utility

Assignee

• Micron Technology, Inc. · US

Inventors

• Zhiping Yin · Boise, US
• Ravi Iyer · Boise, US
• Thomas R. Glass · Idaho City, US
• Richard Holscher · Boise, US
• Ardavan Niroomand · Boise, US
• Linda K. Somerville · Waterbury, US
• Gurtej S. Sandhu · Boise, US

Key dates

• Filing date: Sep 3, 1998
• Grant date: Aug 28, 2001
• Expiry date: Sep 3, 2018

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/32139
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

In one aspect, the invention includes a semiconductor processing method comprising a) forming a metal silicide layer over a substrate; b) depositing a layer comprising silicon, nitrogen and oxygen over the metal silicide layer; and c) while the layer comprising silicon, nitrogen and oxygen is over the metal silicide layer, annealing the metal silicide layer. In another aspect, the invention includes a gate stack forming method, comprising a) forming a polysilicon layer over a substrate; b) forming a metal silicide layer over the polysilicon layer; c) depositing an antireflective material layer over the metal silicide layer; d) forming a silicon nitride layer over the antireflective material layer; e) forming a layer of photoresist over the silicon nitride layer; f) photolithographically patterning the layer of photoresist to form a patterned masking layer from the layer of photoresist; and g) transferring a pattern from the patterned masking layer to the silicon nitride layer, antireflective material layer, metal silicide layer and polysilicon layer to pattern the silicon nitride layer, antireflective material layer, metal silicide layer and polysilicon layer into a gate stack. In …