Three-dimensional ferroelectric capacitor structure for nonvolatile random access memory cell
US6281535A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 22, 1999 |
| Grant date | Aug 28, 2001 |
| Priority date | — |
| Expiry date | Jan 22, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/716
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A capacitor structure or an array of capacitors and a method of fabricating the structure utilize the contours of a cavity created in a layer stack to form two three-dimensional electrode plates. The three-dimensional electrode plates reduce the lateral size of the capacitor structure. The fabrication of the capacitor structure is compatible to conventional CMOS processing technology, in which the resulting capacitor structure may become embedded in a CMOS device. As an example, the capacitor structure may be fabricated along with a MOS transistor to produce a one-transistor-one-capacitor nonvolatile memory cell. Preferably, the three-dimensional electrode plates are made of platinum (Pt) or iridium (Ir) and the capacitor dielectric is a ferrous-electric material, such as lead-zirconate-titanate (PZT) or barium-strontium-titanate (BST). The electrode plates and the capacitor dielectric are formed by depositing layers of appropriate materials within the cavity, which has been formed to include tapering walls in a dielectric layer of the layer stack. Next, portions of the deposited layers, or a "capacitor stack," are removed down to the surface of the dielectric layer such that only …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.