Multiprocessor system bus with a data-less castout mechanism
US6282615A · kind A · utility
41Cited by
2References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 9, 1999 |
| Grant date | Aug 28, 2001 |
| Priority date | — |
| Expiry date | Nov 9, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0804
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for casting out data within a cache memory hierarchy for a data processing system is disclosed. The data processing system has multiple processing units, each of the processing units having a multi-level cache memory hierarchy. In response to a castout write request from a cache memory to a non-inclusive lower-level cache memory within a cache memory hierarchy, the data transfer is aborted if the lower-level cache memory already has a copy of the data of the castout write. The coherency state of the lower-level cache memory is then updated, if necessary.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.