Performing optical proximity correction with the aid of design rule checkers
US6282696A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 9, 1999 |
| Grant date | Aug 28, 2001 |
| Priority date | — |
| Expiry date | Mar 9, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F7/70441
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A method is disclosed for identifying regions of an integrated circuit layout design where optical proximity correction will be most useful and then performing optical proximity correction on those regions only. More specifically, the method includes the following steps: (a) analyzing an integrated circuit layout design with a design rule checker to locate features of the integrated circuit layout design meeting predefined criteria; and (b) performing optical proximity correction on the features meeting the criteria in order to generate a reticle design. The criteria employed by the design rule checker to select features include outside corners on patterns, inside corners on features, feature size, feature shape, and feature angles.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.