Method to implement flash memory
US6285584A · kind A · utility
5Cited by
11References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 23, 2001 |
| Grant date | Sep 4, 2001 |
| Priority date | — |
| Expiry date | Jan 23, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A plurality of flash electrically erasable programmable read only memory (EEPROM) cells is disclosed wherein metal lines couple both the sources and the drains of the flash cells. Reading of these flash cells is accomplished by applying a positive voltage to the source and reading from the associated metal source line. A soft erase scheme for increasing the threshold voltage of over-programmed flash cells is provided that prevents the leakage caused by applying a positive voltage to the drain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.