Erase scheme to tighten the threshold voltage distribution of EEPROM flash memory cells
US6285588A · kind A · utility
28Cited by
3References
10Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 31, 2000 |
| Grant date | Sep 4, 2001 |
| Priority date | — |
| Expiry date | Jan 31, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3404
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method to tighten the threshold voltage distribution curve in a memory device during a negative gate source erase by applying 5 volts to the sources of all the memory cells in the memory device, allowing the drains to float and applying a negative pulse followed by a positive pulse to all the control gates of all the memory cells in the memory device. During a negative gate channel erase, the drains and sources are allowed to float, the p-well is biased at plus 5 volts and a negative pulse followed by a positive pulse is applied to all the control gates of all the memory cells in the memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.