Decoded source lines to tighten erase Vt distribution
US6285599A · kind A · utility
16Cited by
5References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 2, 2000 |
| Grant date | Sep 4, 2001 |
| Priority date | — |
| Expiry date | May 2, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A flash memory device and a method to erase the flash memory device having a plurality of memory cells each having a source, a drain, a control gate, wherein the memory cells are organized in rows and columns with a wordline attached to the control gates of the memory cells in a row, with a bitline attached to the drains of cells in a column and a sourceline attached to the sources of cells in a row, and a switch connected between each sourceline and V.sub.S is controlled by sourceline decode circuit that opens a sourceline switch after the cells on the associated wordline verify as erased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.