Patent · US Expired

Integrated memory having redundant units of memory cells, and test method for the redundant units

US6285605A · kind A · utility

3Cited by

3References

2Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Peter Schrogmeier · Hersbruck, DE
Stefan Dietrich · Potsdam, DE
Sabine Schoniger · Hersbruck, DE
Christian Weis · Scheidegg, DE

Key dates

Filing date	May 30, 2000
Grant date	Sep 4, 2001
Priority date	—
Expiry date	May 30, 2020

Classification

Technology area (CPC G)Physics
CPC primaryG11C29/24
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Each redundant unit of an integrated memory device is assigned respective programmable elements, comparison units, a code converting unit, a logic unit and a multiplexer. Each multiplexer has a first switching state, in which it connects outputs of the first comparison units to first inputs of the logic unit, and a second switching state, in which it connects outputs of the code converting unit to the first inputs of the logic unit. In the second switching state of the multiplexers, each redundant unit is assigned a different address in the unprogrammed state of the programmable elements. Therefore, redundant units can be selected individually for test purposes.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.