Method of forming a MISFET device with a bit line completely surrounded by dielectric
US6287914A · kind A · utility
11Cited by
8References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 17, 2000 |
| Grant date | Sep 11, 2001 |
| Priority date | — |
| Expiry date | Aug 17, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/485
Abstract
A memory cell of a DRAM is reduced in size by making the width of a bit line finer than the minimum size determined by the limit of resolution of a photolithography. The bit line is made fine by forming a silicon oxide film on the inside wall of a wiring trench formed in a silicon oxide film and by forming the bit line inside the silicon oxide film. The silicon oxide film formed in the trench is deposited so that the silicon oxide film has a thickness thinner than half the width of the wiring trench and in the fine gap inside the silicon oxide film is buried a metal film to be the material of the bit line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.