Process for forming a combination hardmask and antireflective layer
US6287951A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 7, 1998 |
| Grant date | Sep 11, 2001 |
| Priority date | — |
| Expiry date | Dec 7, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76895
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A hardmask layer (34) is formed over insulating layers (26, 24, 22 and 20), and an antireflective layer (36) is formed overlying the hardmask layer (34). A resist layer (38) is formed overlying the antireflective layer (36), and an opening is formed in the resist layer to expose a surface portion of the antireflective layer (36). The exposed surface portion of the antireflective layer (36) and portions of the hardmask layer (34) are etched to expose a surface portion of the insulating layers (26, 24, 22 and 20), and a feature opening (61) is formed in the insulating layers (26, 24, 22 and 20). A conductive material (74) is deposited to fill the feature opening (61), and portions of the conductive material (74) lying outside the opening are removed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.