Kevin Lucas
22Patents
14h-index
44Co-inventors
81Inventor score
Filing activity: Apr 15, 1996 → Nov 9, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5741626A | Method for forming a dielectric tantalum nitride layer as an anti-reflective coating (ARC) | Electricity | 232 | Expired |
| US5900340A | One dimensional lithographic proximity correction using DRC shape functions | Physics | 222 | Expired |
| US6174810A | Copper interconnect structure and method of formation | Electricity | 175 | Expired |
| US6287951A | Process for forming a combination hardmask and antireflective layer | Electricity | 99 | Expired |
| US5849440A | Process for producing and inspecting a lithographic reticle and fabricating semiconductor devices using same | Physics | 67 | Expired |
| US8175737B2 | Method and apparatus for designing and integrated circuit | Physics | 57 | Active |
| US6004850A | Tantalum oxide anti-reflective coating (ARC) integrated with a metallic transistor gate electrode and method of formation | Electricity | 52 | Expired |
| US5920487A | Two dimensional lithographic proximity correction using DRC shape functions | Physics | 45 | Expired |
| US8312394B2 | Method and apparatus for determining mask layouts for a spacer-is-dielectric self-aligned double-patterning process | Physics | 40 | Active |
| US5958635A | Lithographic proximity correction through subset feature modification | Emerging Cross-Sectional Technologies | 38 | Expired |
| US5827625A | Methods of designing a reticle and forming a semiconductor device therewith | Physics | 29 | Expired |
| US6989229B2 | Non-resolving mask tiling method for flare reduction | Electricity | 22 | Expired |
| US6294820A | Metallic oxide gate electrode stack having a metallic gate dielectric metallic gate electrode and a metallic arc layer | Electricity | 17 | Expired |
| US6783904B2 | Lithography correction method and device | Physics | 16 | Expired |
| US7284231B2 | Layout modification using multilayer-based constraints | Physics | 12 | Expired |
| US6649452B2 | Method for manufacturing a lithographic reticle for transferring an integrated circuit design to a semiconductor wafer | Physics | 6 | Expired |
| US7962868B2 | Method for forming a semiconductor device using optical proximity correction for the optical lithography | Physics | 3 | Active |
| US8370773B2 | Method and apparatus for designing an integrated circuit using inverse lithography technology | Physics | 3 | Active |
| US7935547B2 | Method of patterning a layer using a pellicle | Physics | 1 | Active |
| US6933227B2 | Semiconductor device and method of forming the same | Electricity | 1 | Expired |
| US6818362B1 | Photolithography reticle design | Physics | 1 | Expired |
| US11900042B2 | Stochastic-aware lithographic models for mask synthesis | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.