Methods for determining on-chip interconnect process parameters
US6291254A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 4, 1999 |
| Grant date | Sep 18, 2001 |
| Priority date | — |
| Expiry date | Feb 4, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method provides estimations of physical interconnect process parameter values in a process for manufacturing integrated circuits. The method includes fabricating test structures each providing a value of a measurable quantity corresponding to a value within a range of values of the physical interconnect process parameters. In some embodiments, the measured value is used to derive the values of the physical interconnect process parameters, either by a numerical method using a field solver, or by a closed-form solution. The values of physical interconnect process parameters involving physical dimensions are also obtained by measuring photomicrographs obtained using a scanning electron microscope from cross sections of test structures. In some embodiments, a family of test structures corresponding to a range of conductor widths and a range of spacings between conductors are measured.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.