Robert G. Mathews
9Patents
8h-index
13Co-inventors
58Inventor score
Filing activity: Sep 25, 1997 → Mar 12, 2003
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6643831B2 | Method and system for extraction of parasitic interconnect impedance including inductance | Physics | 237 | Expired |
| US6591407B1 | Method and apparatus for interconnect-driven optimization of integrated circuit design | Physics | 85 | Expired |
| US6381730B1 | Method and system for extraction of parasitic interconnect impedance including inductance | Physics | 59 | Expired |
| US6057171A | Methods for determining on-chip interconnect process parameters | Electricity | 32 | Expired |
| US6291254A | Methods for determining on-chip interconnect process parameters | Electricity | 29 | Expired |
| US6312963A | Methods for determining on-chip interconnect process parameters | Electricity | 25 | Expired |
| US6403389B1 | Method for determining on-chip sheet resistivity | Electricity | 23 | Expired |
| US7222311B2 | Method and apparatus for interconnect-driven optimization of integrated circuit design | Physics | 23 | Expired |
| US6311312A | Method for modeling a conductive semiconductor substrate | Physics | 1 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.