Cross coupled thin film transistors and static random access memory cell
US6291276A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 19, 1998 |
| Grant date | Sep 18, 2001 |
| Priority date | — |
| Expiry date | Aug 19, 2018 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/903
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A pair of thin film transistors formed in adjacent layers of polysilicon. The gate of the first TFT and the source, drain and channel regions of the second TFT are formed in the first polysilicon layer. The source, drain and channel regions of the first TFT and the gate of the second TFT are formed in the second polysilicon layer. A dielectric layer is interposed between the first and second polysilicon layers. The first TFT gate overlaps the second TFT drain region in the first polysilicon layer and the second TFT gate overlaps the first TFT drain region in the second polysilicon layer. In another aspect of the invention, two TFTs are incorporated into a SRAM memory cell. The memory cell includes: (i) a bit line; (ii) an access transistor having a first source/drain and a second source/drain, the first source/drain being electrically connected to the bit line; (iii) a parasitic diode formed between the second source/drain of the access transistor and the substrate; (iv) a pull down transistor having a source, drain, channel and gate; (v) a first TFT having a source, drain, channel and gate, the first TFT gate being coupled to a power supply voltage V.sub.cc through an active load …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.