Fabrication method of a gate junction conductive structure
US6291301A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 19, 1999 |
| Grant date | Sep 18, 2001 |
| Priority date | — |
| Expiry date | Jul 19, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/662
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a gate junction conductive structure is described in which a selective silicon deposition method is used to form a silicon layer of a greater area on the polysilicon gate. A metal silicide process is further conducted on the silicon layer to convert the silicon layer to a metal silicide layer. Since the gate junction surface in forming the metal silicide layer is increased, not only the narrow line effect is prevented, the temperature for the thermal treatment process in forming the metal silicide layer is also lower. As a result, the sheet resistance of the metal silicide layer is lower and the device is more stable.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.