Locally folded split level bitline wiring

US6291335A · kind A · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Rainer Florian Schnabel · Weilmünster, DE
• Ulrike Gruening · Wappingers Falls, US
• Thomas Rupp · Stormville, US
• Gerhard Mueller · Meitingen, DE

Key dates

• Filing date: Oct 4, 1999
• Grant date: Sep 18, 2001
• Expiry date: Oct 4, 2019

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/485
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A method for fabricating a semiconductor memory with a split level folded bitline structure consisting of three contact levels, in accordance with the present invention includes forming gate structures for transistors in an array region and a support region of a substrate. First contacts are formed down to diffusion regions between the gate structures in the array region. The first contacts have a height which is substantially the same for all first contacts in the array region. Second contacts are formed between first level bitlines in the array region and a first portion of the first contacts, while forming second contacts to a first metal layer from the gate structures and diffusion regions in the support region. Third contacts are formed between second level bitlines in the array region and a second portion of the first contacts, while forming third contacts to a second metal layer from the first metal layer in the support region.