Column redundancy scheme for bus-matching fifos
US6292013A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 15, 1999 |
| Grant date | Sep 18, 2001 |
| Priority date | — |
| Expiry date | Sep 15, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/70
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit and method comprising a multiplexer circuit, a select circuit and a buffer circuit. The multiplexer circuit may be configured to present a data bit in response to a first control signal. The select circuit may be configured to generate one or more first outputs in response to (i) the data bit and (ii) one or more first select signals. The buffer circuit may be configured to present one or more second outputs on a data bus in response to (i) the one or more first outputs and (ii) one or more second control signals. One of the second outputs may have a data state and the rest of the second outputs may have a high impedance state. The first and select signals may be generated by a logic circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.