Processing unit having independent execution units for parallel execution of instructions of different category with instructions having specific bits indicating instruction size and category respectively
US6292845A · kind A · utility
18Cited by
18References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 26, 1998 |
| Grant date | Sep 18, 2001 |
| Priority date | — |
| Expiry date | Aug 26, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3836
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An instruction fetching unit is described for loading instructions from a memory processed by a data processing device. The instruction code can be of at least two different lengths, and each instruction contains at least a single bit indicating said instruction sizes. An instruction buffer coupled with an instruction size evaluation unit for determining the instruction size upon said at least single bit of said instruction is provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.