Alignment techniques for epitaxial growth processes
US6294018A · kind A · utility
284Cited by
5References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 15, 1999 |
| Grant date | Sep 25, 2001 |
| Priority date | — |
| Expiry date | Sep 15, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/85
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The specification describes a lithographic technique in which alignment marks are defined in a first semiconductor layer and the alignment marks are then covered with a protective SiO.sub.2 layer. After subsequent semiconductor layer growth steps, which selectively deposit on the former semiconductor layer but not on the protective layer, the alignment marks remain undistorted and visible to the exposure tool for subsequent processing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.