Method to rework device with faulty metal stack layer
US6297065A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 12, 1999 |
| Grant date | Oct 2, 2001 |
| Priority date | — |
| Expiry date | Jan 12, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing semiconductor wafers wherein a metal layer is formed on a surface of a layer of interlayer dielectric on a partially completed semiconductor wafer and if it is determined that the metal layer is faulty, the faulty metal layer is removed, the surface of the layer of interlayer dielectric is lowered below the tops of metal plugs formed in the layer of interlayer dielectric, the tops of the metal plugs are planarized to the surface of the layer of interlayer dielectric and the metal layer is reformed on the surface of the interlayer dielectric. If the metal layer is determined to be good, the metal layer is etched. If the metal etch is faulty, the metal layer is removed, the layer of interlayer dielectric is reduced to below the tops of plugs formed in the layer of interlayer dielectric, the tops of the metal plugs are planarized down to the surface of the layer of interlayer dielectric and the layer of metal is reformed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.