Method of forming buried straps in DRAMs
US6297089A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 23, 1999 |
| Grant date | Oct 2, 2001 |
| Priority date | — |
| Expiry date | Nov 23, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/0385
Abstract
A conventional initial deep trench structure consists of a patterned Si.sub.3 N.sub.4 pad layer coated silicon substrate with deep trenches formed therein. The trenches are partially filled with doped polysilicon (POLY1). A dielectric film is interposed between said polysilicon fill and the substrate to create the storage capacitor. A TEOS SiO.sub.2 collar layer conformally coats the upper portion of the structure. Now, the TEOS SiO.sub.2 is dry etched in a two-step process performed in the same RIE reactor. In the first step, the TEOS SiO.sub.2 is etched at least 6 times faster than the Si.sub.3 N.sub.4 (stopping on the Si.sub.3 N.sub.4 pad layer). In the second step, the operating conditions ensure a partially isotropic dry etch, preferably with twice the power and 1.25 times the pressure, thus providing a vertical etch rate 6.times. the horizontal rate. As a result of this step, the upper part of the silicon substrate in the trench is exposed without damages. Next, N-type dopant is implanted in the upper portion of the silicon substrate to create a doped region. The trench is filled with a layer of doped polysilicon (POLY2) which is planarized by chemical-mechanical polishing do…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.