Method for forming silicide regions on an integrated device
US6297135A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 21, 1998 |
| Grant date | Oct 2, 2001 |
| Priority date | — |
| Expiry date | Sep 21, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invented method can be used to form silicide contacts to an integrated MISFET device. Field isolation layers are formed to electrically isolate a portion of the silicon substrate, and gate, source and drain regions are formed therein. A polysilicon runner(s) that makes an electrical connection to the integrated device, is formed on the isolation layers. The structure is subjected to ion implantation to amorphized portions of the silicon gate, source, drain and runner regions. A metal layer is formed in contact with the amorphized regions, and the metal layer overlying the active region of the integrated device is selectively irradiated using a mask. The light melts part of the gate, and amorphized source and drain regions while the remaining portions of the integrated device and substrate remain in their solid phases. Metal diffuses into the melted gate, source and drain regions which are thus converted into respective silicide alloy regions. Preferably, during selective irradiation, a portion of the gate region is not exposed to light so that it is relatively cool and acts as a heat sink to draw heat away from the irradiated portion of the gate region. The heat sink effect cau…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.