Dual damascene interconnect structure with reduced parasitic capacitance
US6297554A · kind A · utility
209Cited by
11References
9Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 10, 2000 |
| Grant date | Oct 2, 2001 |
| Priority date | — |
| Expiry date | Mar 10, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An improved structure of a dielectric layer between two adjacent copper wiring lines is disclosed. The dielectric layer is composed of silicon oxide and the adjacent copper wiring lines are formed using a dual damascene process. The structure of the dielectric layer according to the present invention comprises at least one trench in the surface of the dielectric layer, an insulating layer in the trench and at least one void in the insulating layer. The void is used to reduce the effective dielectric constant as well as the parasitic capacitance of the dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.