Memory cell configuration and method for its production
US6300652A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 22, 1996 |
| Grant date | Oct 9, 2001 |
| Priority date | — |
| Expiry date | Nov 22, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/692
Abstract
A memory cell configuration and a method for its production include stacked capacitors and use a vertical storage capacitor having a ferroelectric or paraelectric storage dielectric. In order to produce the storage capacitor, a dielectric layer for the storage dielectric is produced over the whole area. The dielectric layer is subsequently structured and first electrodes and second electrodes for the storage capacitors are formed. The invention is suitable for Gbit DRAMs and for nonvolatile memories.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.