Content addressable memory cell with a bootstrap improved compare
US6301140A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 25, 2000 |
| Grant date | Oct 9, 2001 |
| Priority date | — |
| Expiry date | Oct 25, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A content addressable memory, CAM, cell wherein the only compare-transfer FETS used are NFETs. The gates of the NFET compare-transfer FETS are driven to a voltage above the positive power supply, VDD. By precharging the bitlines to the negative power supply voltage, GND, the gate of one of the compare-transfer NFETS is driven above VDD when a bitline transitions from a "low" value to a "high" value. The capacitance between the bitline being driven high and the gate of a compare-transfer NFET couples the gate higher than VDD. This bootstrapping technique improves the compare access time of a CAM. In addition, this technique reduces the capacitance on the bitlines resulting in faster read and write access times and reduces the physical size of the CAM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.