Method for fabricating a buried bit line in a DRAM cell
US6303424A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 21, 1999 |
| Grant date | Oct 16, 2001 |
| Priority date | — |
| Expiry date | Oct 21, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/033
Abstract
A fabrication method for a dynamic random access memory is described, wherein after the formation of the shallow trench in the substrate to define the active region, an isolation structure is formed in the shallow trench. A first conductive layer is formed to cover the substrate and to fill the shallow trench. A portion of the first conductive layer is removed, leaving only the portion in the shallow trench to form a bit line in the shallow trench. Thereafter, an elevated portion is formed on the substrate, connecting the bit line to the active region where the source region is to be formed. A transistor is then formed in the active region. The area of the source region of the transistor includes the substrate under the elevated part, wherein the source region is connected to the second conductive layer. A dielectric layer is further formed covering the substrate, followed by forming a capacitor on the dielectric layer, wherein the capacitor passes through the dielectric layer to connect with the transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.