Shielded bit line architecture for memory arrays
US6304479A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Jun 23, 2000 |
| Grant date | Oct 16, 2001 |
| Priority date | — |
| Expiry date | Jun 23, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory array, in accordance with the invention, includes a plurality of memory cells disposed in an array. A plurality of bitlines are included for reading and writing data to and from the memory cells. The plurality of bitlines include a first group of bitlines and a second group of bitlines. Each bitline of the first group is interposed between bitlines of the second group, and each bitline of the second group is interposed between bitlines of the first group. The first group of bitlines are active when the second group of bitlines are inactive, and the second group of bitlines are active when the first group of bitlines are inactive such that adjacent inactive bitlines provide a shield to prevent cross-coupling between active bitlines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.