Patent · US Expired

Integrated memory with two burst operation types

US6310824A · kind A · utility

3Cited by

9References

4Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Sabine Schoniger · Hersbruck, DE
Peter Schrogmeier · Hersbruck, DE
Christian Weis · Scheidegg, DE
Stefan Dietrich · Potsdam, DE

Key dates

Filing date	Sep 14, 2000
Grant date	Oct 30, 2001
Priority date	—
Expiry date	Sep 14, 2020

Classification

Technology area (CPC G)Physics
CPC primaryG11C7/1018
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

The memory has a bidirectional address counting unit C1; S, which performs a counting operation for the purpose of generating internal column addresses from an external column address A7 . . . 0. In this case, the counting direction is dependent on the burst operating mode and on an address bit A1 of the external column address. Moreover, the memory has a transformation unit C2; SR2, which forwards partial addresses A2 . . . 1'; PA3 . . . 0' generated by the address counting unit C1; S either unchanged or incremented by the value 1 to the second column decoder CDEC2, in a manner dependent on the burst operating mode and a further address bit A0 of the external column address A7 . . . 0.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.