X-Y grid tree clock distribution network with tunable tree and grid networks
US6311313A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 1998 |
| Grant date | Oct 30, 2001 |
| Priority date | — |
| Expiry date | Dec 29, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An X-Y grid tree clock distribution network for distributing a clock signal across a VLSI chip. Tunable wiring tree networks are combined with an X-Y grid vertically and horizontally connecting all the tree end points. No drivers are necessary at connection points of the tree end points to the X-Y grid. The final X-Y grid distributes the clock signal close to every place it is needed, and reduces skew across local regions. A tuning method allows buffering of the clock signal, while minimizing both nominal clock skew and clock uncertainty. The tuned tree networks provide low skew even with variations in clock load density and non-ideal buffer placement, while minimizing the number of buffers needed. The tuning method first represents a total capacitance of one or more of clock pin loads and twig wiring as a clustered grid load. Next, a smoothing of the clustered grid loads approximates the effect of the X-Y grid. Electrical simulation models are created for network components and clustered grid loads are substituted with smoothed clustered grid loads. A set of N.sub.SECTOR electrical net lists are next created by extracting a net list with associated X-Y grid wires cut to isolate ea…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.