Designing integrated circuit gate arrays using programmable logic device bitstreams
US6311316A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 14, 1998 |
| Grant date | Oct 30, 2001 |
| Priority date | — |
| Expiry date | Dec 14, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods of designing integrated circuit gate arrays include the step of generating a netlist for a gate array integrated circuit having at least first logic and signal resources therein, directly from bitstream data which characterizes a programmable logic device having a first operational functionality and the first logic and signal resources as well. The generating step is also followed by the step of using the netlist to configure the first logic and signal resources within the gate array integrated circuit to provide the first functionality. A preferred integrated circuit design system is also provided and includes a programmable logic device having pre-programmed logic and signal resources therein and a gate array device having base logic and signal resources therein which are equivalent to the unprogrammed logic and signal resources of the programmable logic device. A computer-based apparatus is also provided for decoding a bitstream that characterizes the programmable logic device having a first operational functionality when programmed, into a netlist that designates electrical connections in the gate array device when wired to have the first operational functionality, and …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.