Semiconductor device with partial passivation layer

US6313538A · kind A · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Christian Zistl · Dresden, DE
• Paul R. Besser · Sunnyvale, US
• Eric M. Apelgren · Austin, US
• Nicholas J. Kepler · San Jose, US
• Srikanteswara Dakshina-Murthy · Wappingers Falls, US

Key dates

• Filing date: Jan 21, 2000
• Grant date: Nov 6, 2001
• Expiry date: Jan 21, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A semiconductor device includes a first dielectric layer, a plurality of conductive interconnections formed in the first dielectric layer, a patterned passivation layer formed above the conductive interconnections, and a second dielectric layer formed above and in contact with the passivation layer and the first dielectric layer. A method for forming a semiconductor device includes providing a base layer, forming a first dielectric layer over the base layer, forming a plurality of conductive interconnections in the first dielectric layer, forming a patterned passivation layer above the conductive interconnections, and forming a second dielectric layer above and in contact with the passivation layer and the first dielectric layer.