Electroplanarization of large and small damascene features using diffusion barriers and electropolishing
US6315883A · kind A · utility
61Cited by
7References
32Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 5, 1999 |
| Grant date | Nov 13, 2001 |
| Priority date | — |
| Expiry date | Oct 5, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32134
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A disclosed electroplanarization process involves "masking" certain regions of a wafer surface during electropolishing. The regions chosen for masking are features of relatively low aspect ratio (i.e., features that are wider than they are deep). The masking is accomplished with a material of relatively low ionic conductivity, which effectively slows or blocks transport of the metal ions produced during electropolishing. Examples of masking materials include concentrated phosphoric acid and certain polymers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.