Method of forming spacers of multiple widths

US6316304A · kind A · utility

Assignee

• Chartered Semiconductor Manufacturing LTD · SG

Inventors

• Yelehanka Ramachandramurthy Pradeep · Singapore, SG
• Jie Yu · Singapore, SG
• Tjin Tjin Tjoa · Singapore, SG
• Kelvin Wei Loong Loh · Singapore, SG

Key dates

• Filing date: Jul 12, 2000
• Grant date: Nov 13, 2001
• Expiry date: Jul 12, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0165

Abstract

A method is described for forming gate sidewall spacers having different widths. The variation in spacer width allows for optimization of the MOSFET characteristics by changing the dimensions of the lightly doped source/drain extensions. The process is achieved using a method where the gate structure, comprising the gate electrode and gate oxide, is formed by conventional techniques upon a substrate. Lightly doped source drain extensions are implanted into the substrate not protected by the gate structure. The exposed substrate and gate structure are then covered with an insulating liner layer. This is followed by an etch stop layer deposition over the insulating liner layer. A first spacer oxide layer is then deposited over the etch stop layer. Areas where thicker spacers are desired are masked, and the unmasked spacer oxide layer is removed. The mask is then stripped away and additional spacer oxide is grown over the entire surface. The result is a thicker oxide in the areas protected by the mask during the previous etch step. The oxide is anisotropically etched and spacers are formed along the gate sidewalls. The spacers are wider in the areas with the thicker oxide. The process…