Method for fabricating a memory cell having a MOS transistor

US6316315A · kind A · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Franz Hofmann · Munich, DE
• Josef Willer · Riemerling, DE

Key dates

• Filing date: Aug 21, 2000
• Grant date: Nov 13, 2001
• Expiry date: Aug 21, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/685

Abstract

A memory cell has a vertical MOS transistor which contains a first electrically insulated gate electrode and a second gate electrode. The second gate electrode is partially disposed in a trench whose sidewall is adjoined by the MOS transistor. The first gate electrode is disposed outside the trench and has a tip at an edge of the trench. The tip enables programming with a reduced current flow. The memory cell can be fabricated by self-aligning fabrication with an area requirement of six F.sup.2.