Multi-state memory
US6317363A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 13, 2000 |
| Grant date | Nov 13, 2001 |
| Priority date | — |
| Expiry date | Oct 13, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5634
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Maximized multi-state compaction and more tolerance in memory state behavior is achieved through a flexible, self-consistent and self-adapting mode of detection, covering a wide dynamic range. For high density multi-state encoding, this approach borders on full analog treatment, dictating analog techniques including A to D type conversion to reconstruct and process the data. In accordance with the teachings of this invention, the memory array is read with high fidelity, not to provide actual final digital data, but rather to provide raw data accurately reflecting the analog storage state, which information is sent to a memory controller for analysis and detection of the actual final digital data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.