Method and system for adaptively adjusting control signal timing in a memory device
US6317381A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 7, 1999 |
| Grant date | Nov 13, 2001 |
| Priority date | — |
| Expiry date | Dec 7, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus is described for selectively adjusting control signal timing in a memory device as a function of the frequency of an externally applied clock signal. The memory device includes clock sensing circuitry that receives the clock signal and responsively produces a plurality of speed signals that transition a plurality of times corresponding in number to the frequency of the clock signal. The memory device also includes a control signal delay circuit that receives a memory command signal and the speed signals, and responsively produces a delayed control signal having a time delay from the command signal corresponding to the number of transitions of the speed signal value. Significantly, the control signal is generated during a period of the clock signal that immediately follows a period of the clock signal when the delay of the control signal delay circuit is set.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.