High-throughput interconnect having pipelined and non-pipelined bus transaction modes
US6317803A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 1996 |
| Grant date | Nov 13, 2001 |
| Priority date | — |
| Expiry date | Sep 27, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1631
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A high throughput memory access port is provided. The port includes features which provide higher data transfer rates between system memory and video/graphics or audio adapters than is possible using standard local bus architectures, such as PCI or ISA. The port allows memory read and write requests to be pipelined in order to hide the effects of memory access latency. In particular, the port allows bus transactions to be performed in either a non-pipelined mode, such as provided by PCI, or in a pipelined mode. In the pipelined mode, one or more additional memory access requests are permitted to be inserted between a first memory access request and its corresponding data transfer. In contrast, in the non-pipelined mode, an additional memory access request cannot be inserted between a first memory access request and its corresponding data transfer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.