Layout method for thin and fine ball grid array package substrate with plating bus
US6319750A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 14, 2000 |
| Grant date | Nov 20, 2001 |
| Priority date | — |
| Expiry date | Nov 14, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K3/0052
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A layout method is proposed for semiconductor package substrate with plating bus, such as TFBGA (Thin & Fine Ball Grid Array) substrate, which can help allow each singulated package unit from the substrate to be substantially free of trace short-circuits due to misaligned cutting during singulation process. The proposed layout method is characterized in the provision of a plating bus of a special layout pattern for interconnecting all the via lands alongside each singulation line. The plating bus includes a plurality of crosswise segments, each being used to to interconnect one crosswise-opposite pair of the via lands across the singulation line; and a plurality of diagonal segments, each being used to interconnect one neighboring pair of the crosswise segments diagonally to each other across the singulation line. The proposed layout method allows each singulated package unit from the substrate to be substantially free of trace short-circuits due to misaligned cutting during singulation process. Moreover, it also allows the layout design work to be less complex than prior art.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.